
# PlanAhead Launch Script for Post-Synthesis pin planning, created by Project Navigator

create_project -name fpga -dir "C:/Users/Shahriar Shahramian/Desktop/32x32LEDMatrix/fpga/planAhead_run_3" -part xc6slx9tqg144-2
set_property design_mode GateLvl [get_property srcset [current_run -impl]]
set_property edif_top_file "C:/Users/Shahriar Shahramian/Desktop/32x32LEDMatrix/fpga/fpga_top.ngc" [ get_property srcset [ current_run ] ]
add_files -norecurse { {C:/Users/Shahriar Shahramian/Desktop/32x32LEDMatrix/fpga} {ipcore_dir} }
set_param project.pinAheadLayout  yes
set_property target_constrs_file "fpga_top.ucf" [current_fileset -constrset]
add_files [list {fpga_top.ucf}] -fileset [get_property constrset [current_run]]
link_design
