uart_top Project Status (09/05/2013 - 22:04:14)
Project File: | fpga.xise | Parser Errors: | No Errors
Module Name: | uart_top | Implementation State: | Translated
Target Device: | xc6slx9-2tqg144 | Errors: |
Product Version: | ISE 14.6 | Warnings: |
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: |  | Final Timing Score: |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report |  |  |  |  |
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
CPLD Fitter Report (Text) |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated

Date Generated: 09/05/2013 - 22:05:03