fpga_top Project Status (08/30/2015 - 00:40:54)
Project File: | fpga.xise | Parser Errors: | No Errors
Module Name: | fpga_top | Implementation State: | Programming File Generated
Target Device: | xc6slx9-2tqg144 | Errors: | No Errors
Product Version: | ISE 14.7 | Warnings: | 8 Warnings (0 new)
Design Goal: | Balanced | Routing Results: | All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: | All Constraints Met
Environment: | System Settings | Final Timing Score: | 0 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 294 | 11,440 | 2% |
Number used as Flip Flops | 294 |  |  |
Number used as Latches | 0 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 0 |  |  |
Number of Slice LUTs | 382 | 5,720 | 6% |
Number used as logic | 366 | 5,720 | 6% |
Number using O6 output only | 272 |  |  |
Number using O5 output only | 25 |  |  |
Number using O5 and O6 | 69 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 11 | 1,440 | 1% |
Number used as Dual Port RAM | 0 |  |  |
Number used as Single Port RAM | 0 |  |  |
Number used as Shift Register | 11 |  |  |
Number using O6 output only | 11 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 0 |  |  |
Number used exclusively as route-thrus | 5 |  |  |
Number with same-slice register load | 3 |  |  |
Number with same-slice carry load | 2 |  |  |
Number with other load | 0 |  |  |
Number of occupied Slices | 126 | 1,430 | 8% |
Number of MUXCYs used | 180 | 2,860 | 6% |
Number of LUT Flip Flop pairs used | 412 |  |  |
Number with an unused Flip Flop | 134 | 412 | 32% |
Number with an unused LUT | 30 | 412 | 7% |
Number of fully used LUT-FF pairs | 248 | 412 | 60% |
Number of unique control sets | 19 |  |  |
Number of slice register sites lost to control set restrictions | 55 | 11,440 | 1% |
Number of bonded IOBs | 19 | 102 | 18% |
Number of LOCed IOBs | 19 | 19 | 100% |
IOB Flip Flops | 8 |  |  |
Number of RAMB16BWERs | 0 | 32 | 0% |
Number of RAMB8BWERs | 9 | 64 | 14% |
Number of BUFIO2/BUFIO2_2CLKs | 1 | 32 | 3% |
Number used as BUFIO2s | 1 |  |  |
Number used as BUFIO2_2CLKs | 0 |  |  |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 2 | 16 | 12% |
Number used as BUFGs | 2 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% |
Number of ILOGIC2/ISERDES2s | 1 | 200 | 1% |
Number used as ILOGIC2s | 1 |  |  |
Number used as ISERDES2s | 0 |  |  |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 200 | 0% |
Number of OLOGIC2/OSERDES2s | 7 | 200 | 3% |
Number used as OLOGIC2s | 7 |  |  |
Number used as OSERDES2s | 0 |  |  |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 128 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 0 | 16 | 0% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 1 | 2 | 50% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 3.62 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Sun Aug 30 01:27:44 2015 | 0 | 3 Warnings (0 new) | 6 Infos (0 new)
Translation Report | Current | Sun Aug 30 01:27:50 2015 | 0 | 0 | 2 Infos (0 new)
Map Report | Current | Sun Aug 30 01:28:22 2015 | 0 | 1 Warning (0 new) | 9 Infos (0 new)
Place and Route Report | Current | Sun Aug 30 01:28:38 2015 | 0 | 3 Warnings (0 new) | 0
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | Sun Aug 30 01:28:46 2015 | 0 | 0 | 3 Infos (0 new)
Bitgen Report | Current | Sun Aug 30 01:28:58 2015 | 0 | 1 Warning (0 new) | 1 Info (0 new)

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | Sun Aug 30 13:40:27 2015
Physical Synthesis Report | Out of Date | Sun Aug 30 01:28:22 2015
Locked Pin Constraints | Out of Date | Thu Sep 5 23:25:54 2013
WebTalk Report | Out of Date | Sun Aug 30 01:28:58 2015
WebTalk Log File | Out of Date | Sun Aug 30 01:29:02 2015

Date Generated: 08/30/2015 - 13:45:05